1. Field of the Invention
The present invention relates to a semiconductor device fabricating method and, more particularly, to a semiconductor device fabricating method for forming an insulation film on an entire main surface of a substrate for the device, including an uneven, patterned surface portion of the main surface.
2. Discussion of the Related Art
With reference to FIGS. 1A through 8, sequential steps of a method of fabricating a DRAM/logic hybrid type semiconductor device of the related art (in the following explanation, a DRAM/logic hybrid type semiconductor device will be termed merely as a “hybrid type semiconductor device” or a “DRAM & logic device”) are explained and the problem mentioned above, of forming a film on an uneven, patterned surface, is explained from a practical standpoint.
FIGS. 1A and 1B are cross-sectional views of structures produced at successive steps a and b, respectively, in the course of fabricating a hybrid type semiconductor device in accordance with a method of the related art. In step a and as shown in FIG. 1A, n-type wells 5 and 6 are formed within active regions 3 and 4, respectively, defined within an element isolating insulation film 2 on a major surface of a silicon substrate 1, the p-type well 7 being formed within the n-type well 6. Moreover, gate electrodes 10, 11, 12 and 13 of corresponding MOS transistors are formed within respective active regions 3 and 4 of the common silicon substrate 1 by sequentially laminating thereon a polysilicon film (10a, 11a, 12a and 13a), a tungsten silicide film (10b, 11b, 12b and 13b) and a silicon nitride film (10c, 11c, 12c and 13c) and then patterning same. Respective source/drain regions 15 and 16 of respective MOS transistors in the active regions 4 and 3 are formed to a shallow depth within the corresponding n-type and p-type wells 6 and 7. On the left and right side of the drawings, relatively to the center, there are schematically illustrated a DRAM part active region 3 and a logic device part active region 4, respectively.
Next, in step b and as shown in FIG. 1B, a silicon nitride film 20 is formed so as to cover the entire surface of the DRAM part active region 3 (left side of figure) and the logic device part active region 4 (right side of FIG. 1B) including the surfaces of gate electrodes 10, 11, 12, 13. The DRAM part active region 3 subsequently is covered with a resist (not shown). The logic active part 4 (right side of FIGS. 1A and 1B) is not covered with the resist and instead is exposed. The silicon nitride film 20 is removed, through an etch-back step using a dry etching process, and a residue thereof designated at 25 on the side surfaces of the gate electrode 10 of the Logic device part 4 is used as a side wall spacer. Thereafter, using the remaining resist, ion implantation is performed for producing diffused source/drain regions 26 in the substrate surface of the Logic device part 4 (right side of FIGS. 1A and 1B). Lastly, the resist used as the mask is removed to provide the structure illustrated in FIG. 1B.
Subsequently, in step c and as shown in FIG. 2A, a cobalt silicide (CoSi) film 30 is formed, using a self-alignment method, selectively on the surface of the source/drain region 15 of the Logic device part 4. Thereafter, a silicon nitride film 33, that is used as a stopper for opening of contact windows, as a post-process, is formed by deposition on the entire surface of the substrate 1, to provide the structure illustrated in FIG. 2A.
In step d and as shown in FIG. 2B, when a BPSG film 35 is formed on the silicon nitride film 33 by a CVD (chemical vapor deposition) method, voids 34 tend to be generated therein, in the portions following the gaps between adjacent gate electrodes 11 and 12 and 12 and 13, because the gate electrode interval (i.e., the spacing between adjacent gates) is small, like a slit, in the DRAM part 3 (left side in the figure).
Subsequently, in step e and as shown in FIG. 3A, the voids 34 are eliminated through reflow annealing of the BPSG film 35. The BPSG film 35 is known to have a merit that it will easily reflow at a comparatively low temperature; however, annealing at 800° C. or higher is required to definitely eliminate the voids 34. This temperature will be explained in more detail when explaining the problem of this process.
Next, in step f as shown in FIG. 3B, contact holes 36, 37 are opened in the BPSG film 35 by a dry etching method in such a manner so as to reach the regions 16 of DRAM device active region 3 of the substrate 1; further, respective contact electrodes 40, 41, consisting of conductive material, are formed within these contact holes 36, 37.
Moreover, in step g and as shown in FIG. 4, a silicon oxide (SiO2) film 45, of a constant, or uniform, thickness, is formed on the entire surface of film 35 and a film 46 is then formed on film 45 by sequentially laminating titanium and titanium nitride layers thereon. Bit lines 47 are then formed, extending through respective patterned openings, or windows, 45′ for electrical connection with the (polysilicon) contact electrodes 40, 41 which extend through respective openings 36 and 37 in the BPSG film 35.
Moreover, in step h, as shown in FIG. 5, a silicon nitride film 49 is deposited on the entire surface of the substrate 1, including the surface of the bit line 47 and film 45. Next, a plasma oxide film 48 is deposited on the bit line 47 by a plasma CVD (chemical vapor deposition) method; the plasma CVD step, however, cuts, or abrads, the silicon nitride film 49 by a sputtering effect of argon gas, and thereby titanium is exposed to the plasma during the plasma CVD process. Accordingly, the exposed surface of titanium is oxidized and titanium oxide 44 is formed, as illustrated in FIG. 5. Subsequently, a further plasma oxide film 48 is deposited so as to cover the entire surface.
Subsequently, in step i and as shown in FIG. 6, a deep contact window 48′ is opened in the plasma oxide film 48, using a dry etching method, to expose the surface of the contact electrode 41, which is not connected with the bit line 47; further, an amorphous silicon plug 50 is formed so as to fill the contact window 48′.
Next, in step j and as illustrated in FIG. 7, a memory cell capacitor is formed in connection with the amorphous silicon plug 50. In this process, a conductive layer is formed on the entire surface of the plasma oxide film 48 and is then patterned to form the storage electrode 51; thereafter, a dielectric material layer is formed on the entire surface, including that of the storage electrode 51, which is then patterned to form the storage layer 52 and a storage electrode layer then is formed on the entire surface and patterned to form an opposing electrode 53, thereby to complete the memory cell capacitor structure. Subsequently, a sufficiently thick plasma oxide silicon film 58 is formed on the entire surface, including that of the memory cell capacitor structure. Thereby, the structure of FIG. 7 is completed.
Next, a metal multilayer-wiring layer forming process is performed, in step k illustrated in FIG. 8. A deep contact window 60 is opened, extending from the surface of the plasma oxide silicon film 58, deposited in the preceding process step j, to the logic device part 4 (right side of the figure). The contact window 60 can be opened by a well-known method combining dry etching with photolithography. After the opening process, a thin barrier metal layer 61 is deposited on the internal bottom and sidewall surfaces of window 60 in such a manner so as to extend up to the external surface of the plasma oxide silicon film 58 and, further, a conductive film 62 (e.g., tungsten) is embedded to form, with the layer 61, both a plug 63 filling the hole 60 and a wiring layer on the surface.
The processes explained above are a summary of the related art. This related art suffers from several problems.
First, in the deposition and forming process of the BPSG film 35 of step d, explained with reference to FIG. 2B, it is attempted to reduce as much as possible the voids, from the initial stage of the film formation, by setting the pressure to a higher value in the course of the film formation process; however, it is known that when the pressure is set to a higher value, the film formation rate is reduced and thus it is impossible to apply, to a mass-production system, the formation of the BPSG film 35 as a thick interlayer insulation film, since the low film formation rate causes the productivity to be too low. Conversely, if the film formation rate is set to a higher value from the beginning, in order to apply this method to a mass-production system, it is considered that the remaining voids can be eliminated, to a large extent, with a sufficient reflow annealing process; however, this is not preferable, because introducing such a sufficient reflow annealing of the BPSG film 35 results in creating the following, different problems.
As one problem, an etch stopper at the time of executing the dry etching step for window opening in the post-process, a nitride film is often used; however, when the BPSG films are arranged at the immediately upper and lower sides of the nitride film and these films are in contact with each other, a stress difference of both BPSG films, relative to the nitride film, is large and the stress is stored in both films and thereby cracks and defects, such as bubbles, are generated in both films.
It is also known that cracks are generated in the plasma nitride silicon film when the BPSG film is placed in direct contact with the plasma nitride silicon film. Accordingly and as a measure for preventing such generation of cracks, when the BPSG film and the plasma nitride silicon film are sequentially laminated, a buffer film is formed at the interface. However, when the BPSG film, buffer film, and plasma nitride silicon film are sequentially formed, the resulting multi-layer film, as a whole, becomes compressive, namely, a compression stress of the film results and, thereby, the center area of film is deflected, swelling somewhat to the upper side. When heat is applied subsequently to this multi-layer film structure, the film as a whole generates a tensile stress and thereby the center area is deflected, swelling somewhat to the lower side. In this case, the BPSG film is reflowed in a heating atmosphere during a reflow annealing step. Subsequently, when the multi-layer structure is cooled to the initial temperature, a tensile stress is generated in the plasma nitride silicon film while the temperature is decreasing, generating a compressive stress in the BPSG film and, thereby, a large stress difference is also generated in the BPSG film. The stress generated during such heating and cooling processes tends to be increased by the presence of the buffer film and, therefore, bubbles are generated within the BPSG film while hardening the BPSG film from a softened state, resulting in the problem that such bubbles remain as a residue within the film while cooling down the film.
As another problem, long-term reflow annealing provides an adverse effect of causing impurity diffusion into the active areas, such as the gate electrode and the like. In the case of a shallow and wide contact window having an aspect ratio (depth to width ratio) of 1 or less, the BPSG film can generally be embedded adequately, and thus without requiring a high temperature reflow annealing for the purpose of eliminating voids, and when heating is conducted at a temperature of about 700° C. in order to obtain a dense film structure, the film can be used directly as an interlayer insulation film. However, with improvements in (i.e., increases in the extent of) miniaturization and integration of devices, it is inevitable that deeper and narrower contact windows having an aspect ratio of 1 or larger are required and, thus, longer reflow annealing processes must be conducted in order to eliminate the voids. Simultaneously, since the area of the element, itself, that has generated unwanted impurity diffusion is also ultra-miniaturized, the adverse effects of impurity diffusion, due to the reflow annealing, are extremely increased.
The problems caused by reflow annealing, explained above, have been considered with a view to eliminate the problems so as to gradually execute the embedding under a higher pressure thereby to make the voids smaller until completion of the embedding of the recess and thereafter to deposit the film at a higher deposition rate under a lower pressure for forming a sufficiently thick film. However, if such a method is introduced for formation of an insulation film including a conductive impurity, such as the BPSG film, by the thermal CVD method, a clear boundary layer is formed at the boundary of the first film, formed under the high pressure process, and the second film, formed later under the low pressure process, in the course of producing the BPSG film. After such a boundary layer is formed, a contact window is opened to the BPSG film, which will become the interlayer insulation film, in order to lay the wiring which is formed to electrically connect the active area in the substrate under the BPSG film; however, the button surface of the window is exposed once to the etchant for surface cleaning to conduct the light wet etching in place of depositing the wiring layer within the contact window. The etchant used in this process penetrates into the boundary layer from the side surface, or edges, of the window and thereby the film tends to be removed later.
For instance, the reflow preferably can be conducted even under a comparatively lower temperature when the BPSG film is formed under a water vapor atmosphere; however, when an annealing process is conducted under a water vapor atmosphere, if a high melting point metal such as tungsten or the like is used as a part of the film, and to prevent oxidation at the surface by the vapor, it is necessary to provide a liner film consisting of a low pressure CVD-silicon nitride film having relatively a higher moisture-proof characteristic (LP-CVD SiN film). However, when a silicon nitride film having a relatively higher dielectric coefficient is provided between the bit lines, it is likely to deteriorate in high-speed operations because a capacitance between the bit lines is increased. Further, there arises a problem in that the liner film, consisting of the silicon nitride film, will interfere with the formation of an idealistic opening of a narrow contact window, resulting in a difficulty, from a technical viewpoint, in simple employment of the process to form the BPSG film under water vapor atmosphere. If a silicon oxide film (HDP-SiO2 film) is formed through high density plasma CVD method, instead of a BPSG film, then the silicon oxide film may be formed around or even below 500° C. However, in the fabricating process using a SiH4—, O2—, Ar-based growth gas, which is generally used to form an HDP-SiO2 film, an inert gas such as Ar or the like, used for the film formation, is suddenly degasificated in the post-annealing process and the film may be removed at the interface with the metal material laminated at the upper part. From another point of view, it has also been considered to introduce a method, aiming at a low film formation temperature, by increasing an impurity concentration of a BPSG film; however, since the moisture absorbing characteristic of a BPSG film is enhanced by a high impurity concentration, the etchant used for the wet etching process, to eliminate a naturally oxidized film, is easily absorbed. As a result, a hydrate of phosphorus, called a “phosphorus ball”, tends to be generated, resulting in the problem that the remaining phosphorus ball changes to a foreign matter that will probably generate pattern failure if such a phosphorus ball is not definitely eliminated, by simply using the wet etch solution processing step.